Electrooptical device

ABSTRACT

In an electrooptical device including an electrooptical modulating layer between a first substrate  101  and a second substrate  105 , all edges  107  to  109  of the first substrate  101  and the second substrate  105 , except an edge where IC chips  110  and  111  are attached, are trued up each other between the first substrate  101  and the second substrate  105 . By this, it is possible to make the area of the first substrate  101  minimum.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an electrooptical device comprisingthin film transistors formed over an insulating substrate and an IC chipformed over the same substrate, particularly to a structure of an activematrix type liquid crystal display device.

2. Description of the Related Art

In recent years, a technique for forming a thin film transistor(hereinafter referred to as a TFT) of a semiconductor thin film formedover a glass substrate has been developed. Moreover, an electroopticaldevice in which a voltage applied to an optical modulating layer heldbetween a pair of substrates is controlled by a TFT to carry out anON/OFF operation of light, has been developed.

Particularly, as a display such as a viewfinder of a video camera or amonitor screen of a note-sized personal computer, the demand for aliquid crystal panel using a liquid crystal as an optical modulatinglayer is rapidly increasing.

At present, the main current of development is a liquid crystal panelconstituted by polysilicon TFTs using crystalline silicon films(typically polysilicon films) as semiconductor thin films. Since theoperating speed of the polysilicon TFT is faster than an amorphoussilicon TFT, it is possible to form a monolithic liquid crystal panel inwhich a pixel matrix circuit and a driving circuit (shift register andthe like) are formed on the same substrate.

Further, it is desired to realize a system-on-panel in which not only adriving circuit such as a shift register but also a logic circuit suchas a clock control circuit, a memory circuit, and a signal conversioncircuit is formed on the same substrate.

Since such a logic circuit requires an operating speed as high as theGHz order, a polysilicon TFT is also required to have an extremely highoperating speed. In order to realize such requirement, it is necessaryto make a circuit element minute according to the scaling law.

However, it is very difficult to form a fine pattern with a wiring widthof 1 μm or less on a generally used large glass substrate. For example,in the glass substrate, there occurs a problem such as undulation andshrinkage of the surface of the substrate. Moreover, it is verydifficult to realize such an optical system as is capable of forming afine pattern in a wide range, so that the formation of a fine pattern isrestricted also by the development of a light exposure technique in anaspect.

Thus, at present, it is the limit to form a driving circuit such as ashift register on the same substrate (nevertheless, the operating speedis insufficient so that divided driving is carried out), and other logiccircuit is provided by an external IC.

SUMMARY OF THE INVENTION

In the present day in which a lightweight, thin, short, and small deviceis desired, the electrooptical device is also required to become smalland lightweight to the utmost. However, even if a driving circuit ismade built-in to increase the functionality of a liquid crystal panel,as long as an external IC is attached to the liquid crystal panel, itanyway becomes an obstacle to making a device miniaturized andlightweight.

The present invention has been made in view of the above problems and anobject of the present invention is to provide an electrooptical devicesuperior in portability and functionality by further systematizing aliquid crystal module.

According to an aspect of the present invention, an electroopticaldevice comprises a first substrate; a second substrate; and anelectrooptical modulating layer disposed between the first substrate andthe second substrate, wherein: a plurality of thin film transistorsconstituting a pixel matrix circuit, a source driving circuit, and agate driving circuit, and at least one IC chip constituting a logiccircuit are disposed on the first substrate; the first substrate and thesecond substrate are bonded to each other in such a manner that alledges except one edge are trued up each other between the firstsubstrate and the second substrate; and the IC chip is attached to thefirst substrate adjacent to the one edge.

According to another aspect of the present invention, an electroopticaldevice comprises a first substrate; a second substrate; and anelectrooptical modulating layer disposed between the first substrate andthe second substrate; wherein: a plurality of thin film transistorsconstituting a pixel matrix circuit, a source driving circuit, and agate driving circuit, and at least one IC chip constituting a logiccircuit are disposed on the first substrate; the first substrate and thesecond substrate are bonded to each other in such a manner that alledges except a portion where an FPC (Flexible Print Circuit) is attachedare trued up each other between the first substrate and the secondsubstrate; and the IC chip is attached to the portion where the FPC isattached.

According to still another aspect of the present invention, anelectrooptical device comprises a first substrate; a second substrate;and an electrooptical modulating layer disposed between the firstsubstrate and the second substrate; wherein: a plurality of thin filmtransistors constituting a pixel matrix circuit, a source drivingcircuit, and a gate driving circuit, and at least one IC chipconstituting a logic circuit are disposed on the first substrate; thefirst substrate is exposed only at a portion where an FPC is attached;and the IC chip is attached to the portion where the FPC is attached.

In the present invention, a liquid crystal layer is disposed between thefirst substrate and the second substrate to form a liquid crystal panel.At this time, although the second substrate is bonded onto the firstsubstrate, edges (side faces) of the respective substrates are trued upeach other, which is the feature of the present invention.

This structure can be obtained by cutting the first substrate and thesecond substrate together, or by cutting at the same position from bothsides of the front and back.

However, only at the portion where the FPC is attached, the firstsubstrate must be exposed by removing the second substrate. Thus, sincethe first substrate is always exposed only at that portion, that portionis effectively used as an attachment portion of IC chips.

The present invention is intended to keep the size of the firstsubstrate to a necessary minimum by effectively using the exposedportion of the first substrate, which is conventionally used only as anattachment portion of an FPC, as an attachment portion of an IC chip.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings;

FIG. 1 is a view showing a structure of a liquid crystal module inEmbodiment 1;

FIG. 2 is a view showing a structure of a liquid crystal module inEmbodiment 2;

FIG. 3 is an enlarged view showing a circuit constituting a liquidcrystal module in Embodiment 3;

FIG. 4 is an enlarged view showing a circuit constituting a liquidcrystal module in Embodiment 4;

FIG. 5 is an enlarged view showing a circuit constituting a liquidcrystal module in Embodiment 5;

FIG. 6 is an enlarged view showing a circuit constituting a liquidcrystal module in Embodiment 6;

FIGS. 7A to 7D are views for explaining manufacturing steps of an activelayer in Embodiment 7;

FIGS. 8A to 8E are views for explaining manufacturing steps of an activelayer in Embodiment 8;

FIGS. 9A to 9E are views for explaining manufacturing steps of an activelayer in Embodiment 8;

FIGS. 10A and 10B are views respectively for explaining a sectionalstructure of a liquid crystal module in Embodiment 9;

FIGS. 11A to 11D are views for explaining manufacturing steps of anactive layer in Embodiment 10;

FIGS. 12A to 12E are views for explaining manufacturing steps of anactive layer in Embodiment 11;

FIG. 13 is an enlarged view showing a circuit constituting a liquidcrystal module in Embodiment 12;

FIG. 14 is an enlarged view showing a circuit constituting a liquidcrystal module in Embodiment 15;

FIG. 15 is a view showing a system structure of a liquid crystal modulein Embodiment 16;

FIG. 16 is a view showing a system structure of a liquid crystal modulein Embodiment 17;

FIG. 17 is a view showing a system structure of a liquid crystal modulein Embodiment 18;

FIGS. 18A and 18B are views respectively showing a system structure of aliquid crystal module in Embodiment 19;

FIG. 19 is a view showing a system structure of a liquid crystal modulein Embodiment 20;

FIGS. 20A to 20C are views respectively showing a system structure of aliquid crystal module in Embodiment 21;

FIG. 21 is a view for explaining a dividing step at multifacedproduction in Embodiment 21; and

FIGS. 22A to 22F are views respectively for explaining an example of anelectronic equipment in Embodiment 22.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will now be describedwith reference to the accompanying drawings.

Embodiment 1

The structure of the present invention will be described with referenceto FIG. 1. FIG. 1 shows a liquid crystal module of the presentinvention. Incidentally, the liquid crystal module means a completedliquid crystal panel equipped with necessary parts (polarizing plate,external IC, etc.). In this embodiment, parts such as a polarizingplate, which do not directly relate to the structure of the presentinvention, are omitted.

In FIG. 1, reference numeral 101 denotes a first substrate. A pixelmatrix circuit 102, a source driving circuit 103, and a gate drivingcircuit 104 are formed by TFTs on the first substrate 101. The TFTincludes a top gate type and a bottom gate type (typically a reversestagger type). Reference numeral 105 denotes a second substrate which isan opposite substrate for holding an electrooptical modulating layer(liquid crystal in this embodiment) against the first substrate 101.

A substrate having an insulating surface is used as each of the firstsubstrate and the second substrate. The substrate having the insulatingsurface includes a glass substrate, a quartz substrate, a ceramicsubstrate, a silicon substrate, and the like in which an under film isprovided. The quartz substrate may be used even if an under film is notprovided.

The feature of the present invention is that the edges of the firstsubstrate 101 and the edges of the second substrate 105 are made asflush as possible. That is, the present invention is characterized inthat the substrates are bonded to each other in such a manner that alledges except one edge are trued up each other.

In this case, it is preferable that the one edge is only one side. Thus,in the case where the first substrate is made of a square glasssubstrate, there is obtained such a state that three edges are trued upeach other between the first substrate and the second substrate, andonly one side is not flush. For example, as shown in FIG. 1, it isdesirable to make flush all edges 107 to 109 except a portion where anFPC 106 is attached.

In the portion where the FPC is attached (portion adjacent to the aboveone edge), since it is necessary to make wiring lines on the firstsubstrate 101 exposed, only the second substrate 105 must be removed. Inthe present invention, for such reason, IC chips 110 and 111 are formedon the exposed first substrate 101 by a COG (chip on glass) method.

There are known two methods of attaching an IC chip by the COG method,that is, a face down method and a face up method (also called a wirebonding method). If the face down method is used in the presentinvention, a device formation surface of the IC chips 110 and 111 isdirected to the side of the first substrate 101. If the face up methodis used, a device formation surface of the IC chips 110 and 111 isdirected to the side of the second substrate 105.

That is, all the edges 107 to 109 of the first substrate 101 and thesecond substrate 105 are trued up each other in the portions except theFPC attaching portion, and the first substrate 101 is exposed only atthe FPC attaching portion. Then the IC chips 110 and 111 are attached tothe exposed portion.

Since in the IC chip, a fine pattern of as deep submicron as 0.35 μm orless (preferably 0.2 μm or less) can be formed, a complicated logiccircuit can be constituted on the chip of several mm square.

The number of IC chips attached to the liquid crystal panel of thepresent invention is not limited to two, but one or plural IC chips maybe provided according to necessity.

By adopting the structure as described above, an occupied area of thefirst substrate 101 can be restricted to a necessary minimum. That is,by effectively using an attaching portion of the FPC of the firstsubstrate 101 as an attaching portion of the IC chip, the size of theliquid crystal panel can be made as small as possible.

In the case where the pixel matrix circuit 102 and the driving circuits103 and 104 are constituted by reverse stagger type TFTs which can bemanufactured at an inexpensive manufacturing cost, the manufacturingcost of the liquid crystal panel main body can be kept low. Like this,by keeping the cost of the liquid crystal panel main body as low aspossible, a product price of the liquid crystal module equipped with ICchips can be lowered.

Further, the structure shown in FIG. 1 has also a meaningful effect inthe manufacturing process of the liquid crystal panel. Normally, in theliquid crystal panel, a plurality of panels are obtained from onesubstrate (called multifaced production) so that a throughput isimproved and a unit price per one liquid crystal panel is lowered. Thus,the effect that the size of the liquid crystal panel can be made minimumas in the present invention, is effective in increasing the number ofpanels which can be formed in one large substrate.

Conventionally, although an external logic circuit formed on a printedboard is connected to a monolithic liquid crystal panel by an FPC toexchange signals, in the present invention, a necessary logic circuit ismade into one chip and is formed on the same substrate. Thus, it ispossible to realize a liquid crystal module very excellent inportability and functionality.

Since the liquid crystal module itself formed on a thin glass substratehas a function as a display device, it is possible to make aminiaturized and lightweight electronic equipment (video camera,portable information terminal, etc.) provided with the liquid crystalmodule.

Embodiment 2

Although an example in which the COG method is used as an attachingmethod of an IC chip is shown in the embodiment 1, a TAB (tape automatedbonding) method may be used. FIG. 2 shows an example of a structure inwhich the TAB method is used.

In FIG. 2, a first substrate 101 and a second substrate 105 are bondedto each other in a manner as described in the embodiment 1. Of course,as described in the embodiment 1, all edges except an FPC attachingportion are trued up each other between the first substrate 101 and thesecond substrate 105, and the first substrate 101 is exposed only at anFPC attaching portion.

In this embodiment, TCPs (tape carrier package) 201 to 203 are attachedto the exposed portion of the first substrate 101. The TCP means such asis obtained by mounting a logic IC on a flexible tape by ganged bonding.Actually, the FPC is the same as the TCP.

If the TAB method is used, the freedom on a mounting surface, such as aconnection pitch, shape, opening structure, and bending structure, isimproved. Thus, the TAB method is suitable for making the connectionpitch fine, and making a liquid crystal module thin, lightweight, andcompact, which accompanies a liquid crystal panel made large volume,highly fine, and colorized.

Embodiment 3

The IC chips 110 and 111 used in the embodiment 1 may be formed ofMOSFETs (also called IGFETs) using a bulk single crystal. FIG. 3 showsan example in which an IC chip using a bulk single crystal is mounted.The structure of a liquid crystal module shown in FIG. 3 is similar tothat of the embodiment 1.

At this time, a source driving circuit 103 and a gate driving circuit104 are constituted by a top gate type TFT (denoted by 10301). FIG. 3shows a CMOS circuit (inverter circuit) in which an N-type TFT and aP-type TFT are complementarily combined with each other. A shiftregister circuit, a buffer circuit, an analog switch circuit, and thelike are normally constituted by the CMOS circuit as a unit.

The CMOS circuit 10301 can be constituted by top gate type TFTs formedby any means.

The IC chips 110 and 111 are constituted by MOSFETs (denoted by 10302)using a bulk single crystal. The MOSFET 10302 is formed by a normal ICforming technique. The detailed description thereof will be omitted inthis embodiment.

In the case where the bulk single crystal is used, since a conventionalIC technique can be followed, an extremely high yield and reliabilitycan be secured. Moreover, an IC chip having high functionality can beattached with a small mounting area.

Embodiment 4

In this embodiment, the source driving circuit 103 and the gate drivingcircuit 104 in the embodiment 3 are constituted by reverse stagger typeTFTs (denoted by 20301). FIG. 4 shows an example in which an IC chipusing a bulk single crystal is used. The structure of a liquid crystalmodule shown in FIG. 4 is similar to that of the embodiment 1.

FIG. 4 shows a CMOS circuit (inverter circuit) in which an N-type TFTand a P-type TFT are complementarily combined with each other. A shiftregister circuit, a buffer circuit, an analog switch circuit, and thelike are normally constituted by the CMOS circuit as a unit.

The CMOS circuit 20301 can be constituted by bottom gate type TFTsformed by any means.

Next, IC chips 20110 and 20111 are constituted by MOSFETs (denoted by20302) using a bulk single crystal. The MOSFET 20302 is formed by anormal IC forming technique. The detailed description thereof will beomitted in this embodiment.

In the case where a bulk single crystal is used as an IC chip, since aconventional IC technique can be followed, an extremely high yield andreliability can be secured. Moreover, an IC chip having highfunctionality can be attached with a small mounting area.

Embodiment 5

In this embodiment, an example in which an IC chip mounted on a liquidcrystal module is formed of an SOI structure, will be described. FIG. 5shows an example in which an IC chip of the SOI structure is mounted.The structure of a liquid crystal panel shown in FIG. 5 is similar tothat of the embodiment 1.

In FIG. 5, a source driving circuit 103 and a gate driving circuit 104are respectively constituted by a CMOS circuit (denoted by 10401),constituted by top gate type TFTs, as a unit circuit. IC chips 10402 and10403 are constituted by FETs (denoted by 10404) of the SOI structure.

In FIG. 5, although the SOI structure denoted by 10404 is an example inwhich transistors are formed on a well-known SIMOX substrate, any otherSOI structure (bonded SOI, SOI using a smart cut method, and the like)can be used. The detailed description of the SOI structure will beomitted.

In the case of the SOI structure, it is possible to constitute a circuitsuperior in an operating speed and reliability to a MOSFET using a bulksingle crystal. It is conceivable that this is caused from decrease ofparasitic capacitance, suppression of a short channel effect, and thelike by thinning an active layer.

It is also possible to attach an IC chip in which a three-dimension alstructure is made by using the SOI technique. In this case, it ispossible to remarkably improve the function of a circuit withoutincreasing a mounting area.

Embodiment 6

In this embodiment, the source driving circuit 103 and the gate drivingcircuit 104 in the embodiment 5 are constituted by bottom gate typeTFTs. FIG. 6 shows an example in which an IC chip of an SOI structure ismounted. The structure of a liquid crystal panel shown in FIG. 6 issimilar to that of the embodiment 1.

In FIG. 6, a source driving circuit 103 and a gate driving circuit 104are respectively constituted by CMOS circuits (denoted by 20401)constituted by reverse stagger type TFTs. IC chips 20402 and 20403 areconstituted by FETs (denoted by 20404) of the SOI structure.

In FIG. 6, although the SOI structure denoted by 20404 is an example inwhich transistors are formed on a well-known SIMOX substrate, any otherSOI structure (bonded SOI, SOI using a smart cut method, and the like)can be used. The detailed description of the SOI structure will beomitted.

In the case of the SOI structure, it is possible to constitute a circuitsuperior in an operating speed and reliability to a MOSFET using a bulksingle crystal. It is conceivable that this is caused from the decreaseof parasitic capacitance, suppression of a short channel effect, and thelike by thinning an active layer.

It is also possible to attach an IC chip in which a three-dimension alstructure is made by using the SOI technique. In this case, it ispossible to remarkably improve the function of a circuit withoutincreasing a mounting area.

Embodiment 7

In this embodiment, a method of forming an active layer of a top gatetype TFT constituting a pixel matrix circuit or a driving circuit on thefirst substrate will be described. Concretely, there is used a means inwhich after an amorphous silicon film is crystallized by a techniquedisclosed in Japanese Patent Laid-open No. Hei. 7-130652, a catalyticelement used for the crystallization is removed. The disclosure isincorporated herein by reference.

First, a quartz substrate 10501 is prepared as a substrate having aninsulating surface. Next, an under film 10502 is formed on the quartzsubstrate 10501. It is preferable to make the under film as flat aspossible. A silicon substrate may be used instead of the quartzsubstrate. In that case, the silicon substrate is subjected to a thermaloxidation process in an atmosphere containing a halide gas, and it isappropriate that a thermal oxidation film is used as an under film.

Next, an amorphous silicon film 10503 is formed. The amorphous siliconfilm 10503 is adjusted so that the final film thickness (film thicknessdetermined after giving consideration to the decrease in the filmthickness after thermal oxidation) becomes 10 to 75 nm (preferably 15 to45 nm). As a film forming method, a low pressure CVD method or a plasmaCVD method may be used.

In that case, it is desirable that the concentration of each of C(carbon) and N (nitrogen) contained in the amorphous silicon film 10503is made less than 5×10¹⁸ atoms/cm³ (typically not larger than 5×10¹⁷atoms/cm³, preferably, not larger than 2×10¹⁷ atoms/cm³), and theconcentration of O (oxygen) is made less than 1.5×10¹⁹ atoms/cm³(typically not larger than 1×10¹⁸ atoms/cm³, preferably not larger than5×10¹⁷ atoms/cm³). Since these impurities may hinder the crystallizationin a subsequent crystallization step, they are not preferable.

Next, a crystallization step of the amorphous silicon film 10503 iscarried out. A technique disclosed in Japanese Patent Laid-open No. Hei.7-130652 by the present inventor is used as a means for crystallization.Although means of both embodiment 1 and embodiment 2 of the publicationmay be used, in this invention, it is preferable to use a techniquedisclosed in the embodiment 2 of the publication (the details of thetechnique are disclosed in Japanese Patent Laid-open No. Hei. 8-78329.The disclosure is also incorporated herein by reference.)

In the technique disclosed in Japanese Patent Laid-open No. Hei.8-78329, a mask insulating film 10504 for selecting added regions of acatalytic element is first formed. Then a solution containing nickel(Ni) as the catalytic element for promoting crystallization of theamorphous silicon film 10503 is applied by a spin coating method to forma Ni containing layer 10505 (FIG. 7A).

As the catalytic element, it is also possible to use cobalt (Co), iron(Fe), palladium (Pd), platinum (Pt), copper (Cu), gold (Au), germanium(Ge), lead (Pb), indium (In) or the like other than nickel.

The adding step of the catalytic element is not restricted to the spincoating method, but it is also possible to use an ion implantationmethod or a plasma doping method using a resist mask. In this case,since it becomes easy to lower an occupied area of an added region andto control a growth distance of a lateral growth region, the methodbecomes an effective technique when a minute circuit is formed.

Next, after the adding step of the catalytic element is ended,dehydrogenating at about 450° C. for 1 hour is carried out, and then aheat treatment is carried out in an inert gas atmosphere, a hydrogenatmosphere, or an oxygen atmosphere at a temperature of 500 to 700° C.(typically 550 to 650° C.) for 4 to 24 hours to crystallize theamorphous silicon film 10503. In this embodiment, a heat treatment at570° C. for 14 hours is carried out in a nitrogen atmosphere.

At this time, crystallization progresses first from nuclei generated ina region 10506 in which nickel was added, and a crystalline region 10507grown almost in parallel to the surface of the substrate 10501 isformed. The crystalline region 10507 is called a lateral growth regionby the present inventors et al. Since individual crystals in the lateralgrowth region are gathered in a state in which they are relativelyuniform, the lateral growth region has an advantage that the totalcrystallinity is excellent (FIG. 7B).

After the heat treatment for crystallization is ended, a heat treatment(gettering process of the catalytic element) for removing or loweringthe catalytic element (nickel) is carried out. In this heat treatment, ahalogen element is made contained in a processing atmosphere, and thegettering effect of the halogen element to a metallic element is used(FIG. 7C).

In order to sufficiently obtain the gettering effect of the halogenelement, it is preferable to carry out the foregoing heat treatment at atemperature exceeding 700° C. If a temperature is not higher than thistemperature, decomposition of a halogen compound in the processingatmosphere becomes difficult, so that there is a fear that the getteringeffect comes not to be obtained. Thus, a heat treatment temperature ismade preferably 800 to 1000° C. (typically 950° C.), and a processingtime is made 0.1 to 6 hours, typically 0.5 to 1 hour.

In a typical example, a heat treatment at 950° C. for 30 minutes iscarried out in an atmosphere of an oxygen atmosphere containing hydrogenchloride (HCl) with a concentration of 0.5 to 10 vol % (in thisembodiment, 3 vol %). If the concentration of HCl is above the foregoingconcentration, unevenness comparable with the film thickness is formedon the surface of the active layer 10508, so that such a highconcentration is not preferable.

As a compound containing a halogen element, other than the HCl gas, akind of or plural kinds of compounds containing halogen elements,selected from the group consisting of HF, NF₃, HBr, Cl₂, ClF₃, BCl₃, F₂,and Br₂ may be used.

In this step, nickel in the lateral growth region 10507 is gettered bythe action of chlorine and is converted into volatile nickel chloride toescape into the air, so that nickel is removed. The concentration ofnickel in a lateral growth region 10508 obtained after this step islowered to 5×10¹⁷ atoms/cm³ or less (typically 2×10¹⁷ atoms/cm³ orless). According to the experience of the present inventor et al, if theconcentration of nickel is 1×10¹⁸ atoms/cm³ or less (typically 5×10¹⁷atoms/cm³ or less), nickel does not have a bad influence on the TFTcharacteristics.

After the gettering process of the catalytic element is ended in themanner described above, patterning of the crystalline silicon film isnext carried out to form an active layer 10509 made of only the lateralgrowth region 10508. Next, a gate insulating film 10510 made of aninsulating film containing silicon is formed. It is appropriate that thethickness of the gate insulating film 10510 is adjusted within the rangeof 20 to 250 nm in consideration of the increase in a subsequent thermaloxidation step as well. Moreover, a well-known vapor phase method(plasma CVD method, sputtering method, etc.) may be used as a filmforming method.

After the gate insulating film 10510 is formed in this way, a getteringprocess of the catalytic element is again carried out. The condition ofthis gettering process may be the same as the foregoing condition. Thecatalytic element is again gettered by this heat treatment, so that theconcentration of the catalytic element remaining in the active layer10509 is further lowered (FIG. 7D).

By this heat treatment, a thermal oxidation reaction progresses in theinterface between the active layer 10509 and the gate insulating film10510 so that the thickness of the gate insulting film 10510 isincreased by a thermal oxidation film. When the thermal oxidation filmis formed in this way, it is possible to obtain asemiconductor/insulating film interface with very few interfaciallevels. Moreover, there is also obtained an effect to prevent inferiorformation (edge thinning) of the thermal oxidation film at the end ofthe active layer.

Further, it is also effective that after the heat treatment in thehalogen atmosphere is carried out, a heat treatment at about 950° C. for1 hour is carried out in a nitrogen atmosphere to improve the filmquality of the gate insulating film 10519.

Incidentally, although two gettering processes are carried out in thisembodiment, even if only either one is carried out, the catalyticelement is sufficiently reduced. For example, if the step shown in FIG.7C is carried out, a heat treatment may be carried out in only an oxygenatmosphere in the subsequent step shown in FIG. 7D.

By the above described steps, it is possible to obtain the active layerextremely excellent in the interfacial characteristics andcrystallinity. Subsequently, it is satisfactory if a TFT is completed bya well-known TFT manufacturing step, and desired circuits such as apixel matrix circuit and a driving circuit are constituted on the samesubstrate.

The top gate type TFT shown in this embodiment has superior electricalcharacteristics as follow.

(1) The subthreshold coefficient indicating switching performance(promptness of switching of on/off operation) of a TFT is as small as 60to 100 mV/decade (typically 60 to 85 mV/decade) for both an N-channelTFT and a P-channel TFT.

(2) The field effect mobility (μ_(FE)) as an index of an operating speedof a TFT is as large as 200 to 650 cm²/Vs (typically 250 to 300 cm²/Vs)for an N-channel TFT, and 100 to 300 cm²/Vs (typically 150 to 200cm²/Vs) for a P-channel TFT.

(3) The threshold voltage (V_(th)) as an index of a driving voltage of aTFT is as small as −0.5 to 1.5 V for an N-channel TFT and −1.5 to 0.5 Vfor a P-channel TFT.

Thus, an electric circuit constituted by the top gate type TFTs of thisembodiment has an extremely high operating speed. Thus, if the electriccircuit is applied to the source driving circuit 103 and the gatedriving circuit 104 formed on the first substrate, it is also possibleto form a shift register circuit which does not require a means such asdivided driving. This is advantageous in making the circuit structuresimple and decreasing an occupied area of the circuit.

Embodiment 8

In this embodiment, an example in which a CMOS circuit is formed bycomplementarily combining an NTFT (N-channel TFT) and a PTFT (P-channelTFT) to constitute a source driving circuit or a gate driving circuit,will be described in the case where a bottom gate type TFT is used.

First, an under film 20502 made of a silicon oxide film is disposed on aglass substrate 20501, and gate electrodes 20503 and 20504 are formedthereon. In this embodiment, although aluminum alloy (aluminum addedwith scandium of 2 wt %) with a thickness of 200 to 400 nm is used asthe gate electrodes 20503 and 20504, chromium, tantalum, tungsten,molybdenum, or polysilicon having conductivity may be used.

Next, the gate electrodes 20503 and 20504 are subjected to anodicoxidation in tartaric acid to form nonporous anodic oxidation films20505 and 20506. The detailed manufacturing method may be referred toJapanese Patent Laid-open No. Hei. 7-135318. The disclosure isincorporated herein by reference. The anodic oxidation films 20505 and20506 protect the gate electrodes 20503 and 20504 against a subsequentprocess temperature.

Then a gate insulating film with a thickness of 100 to 200 nm is formedthereon. A silicon oxide film, a silicon nitride film, or a laminationfilm of the silicon oxide film and silicon nitride film is used as thegate insulating film 20507. In this embodiment, the anodic oxidationfilms 20505 and 20506 also function as parts of the gate insulatingfilm.

Next, an amorphous silicon film 20508 with a thickness of 10 to 150 nm(preferably 10 to 75 nm, more preferably 15 to 45 nm) is formed. Asemiconductor thin film mainly containing silicon (for example, silicongermanium compound expressed by Si_(X)Ge_(1-X) (o<X<1)) may be usedother than the amorphous silicon film.

After the state shown in FIG. 8A is obtained in this way, irradiation oflaser light or intense light having intensity comparable with the laserlight is carried out to crystallize the amorphous silicon film 20508.Excimer laser light is preferable as the laser light. A pulse laser witha light source of KrF, ArF, or XeCl may be used as an excimer laser.

Intense light from a halogen lamp or a metal halide lamp, infraredlight, or intense light from a ultraviolet light lamp may be used as theintense light with intensity comparable with the laser light.

In this embodiment, after the amorphous silicon film 20508 isdehydrogenated, the substrate is scanned with laser light configuredinto a linear shape from one end of the substrate to the other end tocrystallize the entire surface of the amorphous silicon film 20508. Atthis time, the sweep speed of the laser light is made 1.2 mm/s, theprocess temperature is made a room temperature, the pulse frequency ismade 30 Hz, and the laser energy is made 300 to 315 mJ/cm² (FIG. 8B).

In this way, as shown in FIG. 8B, a crystalline silicon film 20509 isobtained. In this embodiment, channel doping is carried out for both aregion which becomes an NTFT and a region which becomes a PTFT so that athreshold voltage is controlled.

In this embodiment, there is shown a structure that an element (forexample, phosphorus) selected from group 15 of the periodic table isadded to the region which becomes the NTFT in order to move thethreshold voltage to a minus side, and an element (for example, boron)selected from group 13 is added to the region which becomes the PTFT inorder to shift the threshold voltage to a plus side.

First, a buffer layer 20510 made of a silicon oxide film and having athickness of 50 to 200 nm (preferably 100 to 150 nm) is formed on thecrystalline silicon film 20508.

Then the region which becomes the PTFT is concealed by a resist mask20511, and phosphorus is added by an ion implantation method (with massseparation) or an ion doping method (without mass separation). Aphosphorus containing region 20512 is formed by this channel dopingstep. Arsenic, antimony or the like may be added instead of phosphorus(FIG. 5C).

At this time, it is appropriate that an acceleration voltage is selectedwithin the range of 5 to 80 KeV (typically 10 to 30 KeV), and a dosageis selected within the range of 1×10¹² to 1×10¹⁷ atoms/cm² (preferably1×10¹³ to 1×10¹⁶ atoms/cm²). In this embodiment, the accelerationvoltage is 30 KeV and the dosage is 5×10¹³ atoms/cm².

The dosage must be experimentally determined in advance. That is, it ispreviously confirmed to what degree the threshold voltage is shifted inthe case where channel doping is not carried out, and it is previouslyobtained what amount of phosphorus is required to be added to obtain adesired threshold voltage. Thus, it is not necessarily required that thedosage must be within the foregoing range.

At this time, since the crystalline silicon film 20509 is very thin, ifion implantation is directly carried out, the film receives seriousdamage so that the crystallinity is lost. In the case where ionimplantation is carried out for a very thin film, control ofconcentration of an impurity is very difficult.

However, in this embodiment, since the doping step becomes throughdoping through the foregoing buffer layer 20510, it is possible tosuppress the damage applied to the crystalline silicon film 20509 at theion implantation. Moreover, since the rather thick buffer layer 20510exists on the crystalline silicon film 20509, it becomes easy to controlthe concentration of an impurity added in the crystalline silicon film20509.

It is preferable to adjust the concentration profile of phosphorus inthe crystalline silicon formed by the ion implantation so that theconcentration of phosphorus becomes low at a portion where a channel isformed (in the vicinity of an interface where the channel formationregion is in contact with the gate insulating film). This effect will bedescribed later.

After the element in group 15 is added into the region which becomes theNTFT in the manner described above, the resist mask 20511 is removed,and a resist mask 20513 is formed to newly conceal the region whichbecomes the NTFT. Next, an element (in this embodiment, boron) selectedfrom group 13 is added into the region which subsequently becomes thePTFT. In this adding step, the foregoing adding step of phosphorus maybe referred to. Of course, gallium, indium or the like may be used otherthan boron (FIG. 8D).

A boron containing region 20514 is formed in the region which becomesthe PTFT by the step shown in FIG. 8D. Also in this case, similarly tothe case of the foregoing adding step of the element in group 15, thebuffer layer 20510 decreases the damage at the ion implantation tofacilitate the control of concentration.

After the above impurity adding step is ended, the buffer layer 20510and the resist mask 20513 are removed, and then patterning is carriedout to form active layers 20515 and 20516. Thereafter, irradiation ofexcimer laser light is carried out to recover from the damage applied atthe ion implantation step and to activate added boron (FIG. 8E).

Next, rear face light exposure is carried out using the gate electrodes20503 and 20504 as masks to form resist masks 20517 and 20518. Animpurity element (typically phosphorus or arsenic) for giving an N typeis added to form a low concentration impurity regions 20519 to 20522with a concentration of about 1×10¹⁷ to 5×10¹⁸ atoms/cm³ (FIG. 9A).

Next, after the resist masks 20517 and 20518 are removed, patterning isagain carried out to form resist masks 20523 and 20524. At this time,the PTFT is completely covered. Then an impurity element for giving an Ntype, the concentration of which is higher than that in FIG. 9A (about1×10¹⁹ to 1×10²⁰ atoms/cm³), is again added to form a source region20525 and a drain region 20526 of the NTFT.

At this time, regions denoted by 20527 and 20528 are ones where theforegoing low concentration regions remain as they are, and the regionssubsequently function as LDD (Light Doped Drain) regions. Further, aregion denoted by 20529 becomes a channel formation region (FIG. 9B).

Next, after the resist masks 20523 and 20524 are removed, resist masks20530 and 20531 are formed so as to completely cover the NTFT at thistime.

An impurity element (typically boron, gallium, or indium) for giving a Ptype is added so that the concentration becomes about 1×10¹⁹ to 1×10²⁰atoms/cm³, and a source region 20532 and a drain region 20533 of thePTFT are formed. A region denoted by 20534 becomes a channel formationregion (FIG. 9C).

Next, after the resist masks 20530 and 20531 are removed, irradiation ofexcimer laser light is carried out to recover from the damage applied atthe ion implantation and to activate the added impurity (FIG. 9D).

After the laser annealing is ended, an interlayer insulating film 20535with a thickness of 300 to 500 nm is formed. The interlayer insulatingfilm 20535 is formed of a silicon oxide film, a silicon nitride film, anorganic resin film, or a lamination film thereof.

Then source electrodes 20536 and 20537 and a common drain electrode20538 made of metallic thin films are formed thereon. A film ofaluminum, tantalum, titanium, tungsten, or molybdenum, or a laminationfilm thereof may be used as the metallic thin film. It is appropriatethat the film thickness is selected within the range of 100 to 300 nm(FIG. 9E).

Finally, the entire is subjected to a heat treatment at a temperature ofabout 350° C. for 2 hours in a hydrogen atmosphere to terminate unpairedbonds with hydrogen. Through the above steps, the CMOS circuit having astructure as shown in FIG. 9E is completed.

A pixel TFT constituting a pixel matrix circuit is completed by formingan interlayer insulating film after the above steps, and by forming apixel electrode electrically connected to a drain electrode.

In the embodiments 1, 2, 4 and 6, the pixel matrix circuit and thedriving circuit are constituted by the reverse stagger type TFTsmanufactured through the steps as described above. However, themanufacturing steps of this embodiment are only an example forconstituting the present invention, and a manufacturing method of thereverse stagger type TFT capable of being used in the present inventionis not limited to this embodiment.

Although channel doping is carried out for the NTFT and the PTFT, it isnot necessary to carry out channel doping if unnecessary.

Even if channel doping is carried out, it is also conceivable to adoptsuch a structure that channel doping is carried out for only the NTFT orPTFT. Moreover, it is also possible to adopt a case where elements ofthe same conductivity are added into both the NTFT and PTFT. Further, anadded element (element in group 15 or element in group 13) may besuitably determined by an operator based on which side the thresholdvoltage is required to be moved between a plus side and a minus side.

Embodiment 9

In this embodiment, there is shown an example of a case employing asemiconductor circuit, instead of an IC chip, using a top gate type TFTexplained in the embodiment 7 or a TFT disclosed in Japanese PatentApplication No. Hei. 8-301249 or Hei. 8-301250. The disclosures areincorporated herein by reference.

Since the top gate type TFT shown in the embodiment 7 or the TFTdisclosed in Japanese Patent Application No. Hei. 8-301249 or Hei.8-301250 has a very high operating speed, it is also possible toconstitute such a logic circuit as is conventionally constituted by anIC chip. Especially, a silicon substrate is used as a substrate, it ispossible to handle the TFT like an IC chip.

At this time, it does not matter if the TFT to be formed on the firstsubstrate is formed by any process. In this embodiment, a crystallinesilicon film obtained by crystallizing an amorphous silicon film by anexcimer laser is used as an active layer. Since such a TFT can bemanufactured by a well-known technique, the explanation of manufacturingsteps will be omitted.

FIGS. 10A and 10B are schematic views showing the state of arrangementon the substrate. In FIG. 10A, 10601 denotes a glass substrate (firstsubstrate), and a pixel matrix circuit 10602 and a source or gatedriving circuit 10603, which are constituted by TFTs formed by theforegoing method, are disposed on the glass substrate. Reference numeral10604 denotes a semiconductor chip constituted by TFTs explained in theembodiment 7 or 8, and is attached by a COG method of a face downsystem.

FIG. 10B shows a case where a semiconductor chip 10604 is attached by aCOG method of a face down system. Reference numeral 10605 denotes abonding wire.

Embodiment 10

In this embodiment, in the structure of the embodiment 9, there is shownan example in which manufacturing steps of the top gate type TFT formedon the first substrate are different. Concretely, an example in which agettering effect by P (phosphorus) is employed to remove a catalyticelement used in the technique disclosed in Japanese Patent Laid-open No.Hei. 7-130652, will be described.

First, as a substrate having an insulating surface, a glass substrate10701 on which an under film 10702 is provided, is prepared. A quartzsubstrate, a ceramic substrate, a silicon substrate or the like may beused instead of the glass substrate.

Next, an amorphous silicon film 10703 with a thickness of 10 to 75 nm(preferably 15 to 45 nm) is formed on the under film. After theamorphous silicon film 10703 is formed, a mask insulating film 10704 isformed, and a nickel containing layer 10705 is formed by a spin coatingmethod (FIG. 11A).

Next, after a dehydrogenating process at about 450° C. for 1 hour iscarried out, a heat treatment at 570° C. for 14 hours is carried out tocrystallize the amorphous silicon film. In this way, a lateral growthregion 10706 is obtained (FIG. 11B).

The steps up to here are the same as the embodiment 7. Next, after themask insulating film 10704 is removed, a resist mask 10707 is formed ona region (gettered region) where nickel is to be removed. A siliconoxide film or the like may be used instead of the resist mask.

Next, an adding step of a P (phosphorus) element is carried out by anion implantation method. This step may be carried out by a plasma dopingmethod. The ion implantation may be carried out under the condition thatthe RF power is 20 W, the acceleration voltage is 5 to 30 KeV (typically10 KeV), and the dosage of the P element is not less than 1×10¹³ions/cm² (preferably 5×10¹³ to 5×10¹⁴ ions/cm²).

Although described later, the optimum condition of the P ionimplantation step is changed by the condition of a heat treatment forgettering, which is subsequently carried out. Thus, an operator mustdetermine the optimum condition from the process viewpoint andeconomical viewpoint. At the present circumstances, the presentinventors consider that it is preferable to make the accelerationvoltage 10 KeV and the dosage 1×10¹⁴ to 5×10¹⁴ ions/cm². This dosagecorresponds to about 8×10¹⁹ to 4×10²⁰ atoms/cm³ in concentration.

By the adding step of the P ion, gettering regions 10708 and 10709 and agettered region 10710 are formed. The gettering regions 10708 and 10709are made amorphous by the impact of implanted ions (FIG. 11C).

After the adding step of the P ion is ended in this way, the resist mask10707 is removed, and then a heat treatment for gettering is carried outto gather nickel in the gettered region 10710 to the gettering regions10708 and 10709. Thus, the gettered region 10711 in which nickel isremoved or lowered can be obtained (FIG. 11D).

At this time, it is appropriate that the heat treatment is carried outin an electric heating furnace and in either one of inert gasatmosphere, hydrogen atmosphere, and oxidizing atmosphere. Also, it isappropriate that the temperature is made not less than 400° C.(preferably 550 to 650° C., however, not exceeding the distortion pointof glass). In addition, it is appropriate that the process time is madenot less than 2 hours (preferably 4 to 12 hours).

In this embodiment, since the top gate type TFT is formed on the glasssubstrate, the heat treatment for gettering is restricted. However, if asubstrate having high heat resistance, such as a quartz substrate or asilicon substrate, is used as the substrate, it is possible to carry outgettering at a higher temperature. If gettering is carried out at a hightemperature, a processing time can be shortened by that, so that suchgettering is effective.

According to experiments by the present inventor, a sufficient getteringeffect can be obtained if the temperature range is made 400 to 1,050° C.(typically 600 to 750° C.) and the processing time is made 1 minute to20 hours (typically 30 minutes to 3 hours). At this time, the upperlimit of the processing temperature is a temperature at which aphosphorus element is not reversely diffused into a gettered region.

If a lateral growth region 107111 obtained in the above step ispatterned, it is possible to obtain an active layer superior incrystallinity and having few surplus impurities. Thereafter, it issatisfactory if a TFT is completed in accordance with a well-known. TFTmanufacturing step.

Since the top gate type TFT manufactured in accordance with the steps ofthis embodiment has also very high operation performance, it is suitablefor constituting a driving circuit and the like.

Embodiment 11

This embodiment shows an example in which when a reverse stagger typeTFT is manufactured on a first substrate, a manufacturing methoddifferent from the embodiment 8 is used. Concretely, explanation will bemade to an example in which a crystalline silicon film is formed by atechnique disclosed in Japanese Patent Laid-open No. Hei. 7-130652, anda catalytic element used at that time is removed by a gettering effectof P (phosphorus).

First, in FIG. 12A, 20801 denotes a glass substrate, 20802 denotes anunder film, 20803 and 20804 denote gate electrodes made of N typeconductive polysilicon films, 20805 denotes a gate insulating film, and20806 denotes an amorphous silicon film. It is possible to use anymaterial shown in the embodiment 8 for the gate electrode.

In this embodiment, a film 20807 containing nickel (hereinafter referredto as a nickel containing layer) is formed on the amorphous silicon film20806. A technique disclosed in Japanese Patent Laid-open No. Hei.7-130652 by the present inventors et al. may be used as a method offorming the nickel containing layer 20807. Although both means ofembodiment 1 and embodiment 2 of the publication may be used, thetechnique disclosed in the embodiment 1 of the publication is used inthis embodiment in view of productivity (FIG. 12A).

As the catalytic element, cobalt (Co), iron (Fe), palladium (Pd),platinum (Pt), copper (Cu), gold (Au), germanium (Ge), lead (Pb),gallium (Ga) or the like may be used instead of nickel.

Although the above publication shows an example in which an adding stepof the catalytic element is carried out by a spin coating method, an ionimplantation method or a plasma doping method may be used. In this case,since an occupied area of an added region is lowered, and control of agrowth distance of a lateral growth region becomes easy, it becomes aneffective technique when a minute circuit is constituted.

Next, after the adding step of the catalytic element is ended,dehydrogenating at about 500° C. for one hour is carried out, and then aheat treatment (furnace annealing) at 500 to 700° C. (typically 550 to650° C.) for 4 to 24 hours is carried out in an inert gas atmosphere, ahydrogen atmosphere, or an oxygen atmosphere to crystallize theamorphous silicon film 20806. In this embodiment, a heat treatment at550° C. for 4 hours is carried out in a nitrogen atmosphere to obtain acrystalline silicon film 20808 (FIG. 12B).

Next, a resist mask 20809 having a plurality of openings is formed. Theopenings are formed at such positions that regions which are notsubsequently used as active layers (are removed) are exposed.

Next, an adding step of phosphorus is carried out by using the resistmask 20809 as a mask. This adding step uses an ion implantation methodor an ion doping method. The adding condition is that the RF power is 20W, the acceleration voltage is 5 to 30 KeV (typically 10 KeV), and thedosage of phosphorus is 1×10¹³ atoms/cm² or more (preferably 5×10¹³ to5×10¹⁵ atoms/cm²).

As a standard of a concentration of added phosphorus, it is appropriatethat phosphorus with a concentration higher than the concentration ofnickel contained in the crystalline silicon film 20808 by one figure ormore is added. Since nickel of about 1×10¹⁹ atoms/cm³ is contained inthe foregoing crystalline silicon film 20808, in this case, it ispreferable to add phosphorus of about 1×10²⁰ atoms/cm³.

In this way, regions (gettering regions) 20810 to 20812 added withphosphorus are formed in parts of the crystalline silicon film 20808(FIG. 12C).

Next, after the resist mask 20809 is removed, a heat treatment forgettering nickel is carried out. By this heat treatment, nickelcontained in the gettered regions 20813 and 20814 are moved and capturedto the gettering regions 20810 to 20812 as shown by arrows (FIG. 12D).

This heat treatment may be furnace annealing in an inert gas atmosphere,a hydrogen atmosphere, an oxygen atmosphere, or an oxidizing atmospherecontaining halogen elements. Besides, it is appropriate that a processtemperature is made 400 to 700° C. (preferably 550 to 650° C.), and aprocess time is made 2 hours or more (preferably 4 to 12 hours). As theprocess temperature becomes high, the process time becomes short and thegettering effect also becomes high. However, it is desirable to make thetemperature 650° C. or less in view of the heat resistance of the glasssubstrate.

After nickel is gettered into the gettering regions 20810 to 20812 inthis way, the crystalline silicon film is patterned to form activelayers 20815 and 20816 made of only the gettered regions 20813 and20814. At this time, since the gettering regions 20810 to 20812 andtheir vicinities contain nickel of high concentration, it is desirablenot to use as an active layer but to completely remove.

It is confirmed by SIMS (secondary ion mass spectroscopy) that theconcentration of nickel existing in the active layers 20815 and 20816obtained through the gettering process is lowered to 5×10¹⁷ atoms/cm³ orless. (The concentration in the present specification is defined as aminimum value of SIMS measurement values.)

In the present circumstances, although it is merely ascertained that thenickel concentration is 5×10¹⁷ atoms/cm³ or less due to the restrictionof detection lower limit, it is considered that the concentrationactually reaches at least about 1×10¹⁴ atoms/cm³. Experimentally, it isknown that if the nickel concentration is 5×10¹⁷ atoms/cm³ or less,nickel does not have an influence on TFT characteristics.

In the manner described above, the state shown in FIG. 12E is obtained.Subsequently, if the steps shown in the embodiment 8 are followed, it ispossible to manufacture a CMOS circuit having a structure as shown inFIG. 12E. Of course, it is also possible to apply the technique of thisembodiment to a pixel TFT constituting a pixel matrix circuit.

Although this embodiment shows an example in which an ion implantationmethod or an ion doping method is used as an adding means of phosphorus,annealing (vapor phase method) in an atmosphere containing phosphorus orgettering (solid phase method) into an insulating film containingphosphorus may be used.

Embodiment 12

In this embodiment, an example where an image sensor is mounted on thesame substrate with respect to the liquid crystal module shown in theembodiment 1, will be described. In the case of this embodiment, animage sensor 10801 (FIG. 13) is formed of a top gate type TFT.

The image sensor 10801 is constituted by a top gate type TFT portion anda photoelectric conversion portion as denoted by 10802. Thephotoelectric conversion portion has a structure that a photoelectricconversion layer 10805 is held between a lower electrode (also serves asa drain electrode of the top gate type TFT) 10803 and an upper electrode10804.

The liquid crystal module as in this embodiment is a system panel inwhich the liquid crystal panel itself has a built-in image sensor and itcan be said that the liquid crystal module has such a structure that theeffect of the present invention can be shown more remarkably. In thiscase, it is also effective to incorporate a control circuit forcontrolling the image sensor 10801 into the IC chips 110 and 111.

Embodiment 13

This embodiment shows an example in which a reverse stagger type TFT isused as a switching element in a part of a liquid crystal module havingthe structure shown in the embodiment 12. An image sensor is constitutedby a reverse stagger type TFT portion and a photoelectric conversionportion.

If the structure as in the present invention is adopted, it is possibleto realize a system panel in which a liquid crystal panel itself has abuilt-in image sensor, so that the effect of the present invention canbe shown more remarkably. In this case, it is also effective toincorporate a control circuit for controlling the image sensor into anIC chip.

Embodiment 14

The present invention can be applied to an EL display device using an ELmaterial (organic EL, inorganic EL) as an electrooptical modulatinglayer. Since the EL display device is a self luminescence type device,it has advantages such as high brightness and a high field angle, and issuitable for the use of a direct view type display.

Since an object of the present invention is to improve portability andfunctionality of an electrooptical device and an electronic equipmentusing the electrooptical device, when the present invention is appliedto the direct view type display, a remarkable effect can be obtained.

Embodiment 15

In this embodiment, an example of a structure of an IC chip in theliquid crystal module having the structure shown in the embodiments 1 to13 and in the EL display device shown in the embodiment 14 will bedescribed with reference to a block diagram shown in FIG. 14. A regionsurrounded by a dotted line is a system structure of the IC chip.Moreover, this embodiment shows an example of a circuit in which afteran analog signal is digital processed, it is converted into an analogsignal and is transmitted to a liquid crystal panel.

Analog signals transmitted from the outside are an R signal 11, a Gsignal 12, a B signal 13, a horizontal synchronization signal 14, and avertical synchronization signal 15. The RGB signals 11 to 13 passthrough an A/D converter 16, a VRAM 17 (performing extension of a timeaxis), a γ correction+polarity inversion circuit 18, and a D/A converter19, and are outputted as analog signals.

During that, a clock pulse and a start pulse corresponding to XGA, SXGAand the like are formed in a clock generator 20 on the basis of thehorizontal synchronization signal 14 and the vertical synchronizationsignal 15, and are sent to the A/D converter 16, the VRAM 17 (performingextension of a time axis), the γ correction+polarity inversion circuit18 and the like. The clock generator 20 is controlled by a controlmicrocomputer 21.

In this way, an R signal 22, a G signal 23, and a B signal 24 as analogsignals in which a necessary process has been ended, are outputted. Asource driving circuit 25, a gate driving circuit 26, and a pixel matrixcircuit 27 are formed of TFTs in the liquid crystal panel. The foregoingR signal 22, G signal 23, and B signal 24 are transmitted to the sourcedriving circuit 25.

Incidentally, the TFT in this embodiment includes both a top gate typeTFT and a bottom gate type TFT.

Embodiment 16

In this embodiment, an example of a structure of an IC chip in theliquid crystal module having the structure shown in the embodiments 1 to13 and in the EL display device shown in the embodiment 14 will bedescribed with reference to a block diagram shown in FIG. 15. Thisembodiment shows an example in which an analog signal is directlytransmitted to a liquid crystal panel.

Since the basic structure has already been described in the embodiment15, only points different from the embodiment 15 will be described.

Analog signals (R signal 11, G signal 12, and B signal 13) transmittedfrom the outside pass through an amplifying circuit 30, a γcorrection+polarity inversion circuit 18, a sample-and-hold circuit 31,and a buffer amplifier 32, and are outputted. In this way, an R signal33, a G signal 34, and a B signal 35 as analog signals in which anecessary process has been completed, are outputted. These signals aretransmitted to a source driving circuit 25.

Embodiment 17

In this embodiment, an example of a structure of an IC chip in theliquid crystal module having the structure shown in the embodiments 1 to13 and in the EL display device shown in the embodiment 14 will bedescribed with reference to a block diagram shown in FIG. 16. Thisembodiment shows an example in which a digital signal is directlytransmitted to a liquid crystal panel.

An R signal 40, a G signal 41, and a B signal 42 are digital signalscorresponding to, for example, 6 to 8 bits. The RGB signals 40 to 42 aresubjected to a necessary process in a VRAM 43 and a γ correction circuit44, are converted into an R signal 45, a G signal 46, and a B signal 47,and are transmitted to a source driving circuit 48. In the case of thisembodiment, it is necessary to make the source driving circuit 48 acircuit structure corresponding to digital signals.

Embodiment 18

In this embodiment, an example of a structure of an IC chip in theliquid crystal module having the structure shown in the embodiments 1 to13 and in the EL display device shown in the embodiment 14 will bedescribed with reference to a block diagram shown in FIG. 17. Thisembodiment shows an example in which a digital signal is temporarilysubjected to an arithmetic process and is transmitted to a liquidcrystal panel.

Since the basic structure has already been described in the embodiment17, in this embodiment, explanation will be made while paying attentionto only different points.

Digitized RGB signals 40 to 42 are subjected to a correction operationprocess in a DSP (digital signal processor) 50. At this time, thecorrection data are stored in a flash memory 51 and are read asrequired.

The video signals subjected to the correction operation are processed bya VRAM 43 and a γ correction circuit 44, are converted into an R signal52, a G signal 53, and a B signal 54, and are transmitted to the sourcedriving circuit 48.

Embodiment 19

In this embodiment, a constructive example of a process for forming RGBsignals inputted into the system structure shown in the embodiments 15to 18 will be described with reference to block diagrams shown in FIGS.18A and 18B. It is possible to mount also a circuit structure of thisembodiment on a liquid crystal panel substrate by making the circuitone-chip.

As shown in FIG. 18A, an NTSC signal 60 is separated by a YC separationcircuit 61 into a Y (brightness) signal 62 and a C (color) signal 63.Those signals are separated by an RGB separation circuit 64 into an Rsignal 65, a G signal 66, and a B signal 67. Here, a horizontalsynchronization signal 68 and a vertical synchronization signal 69 areformed.

A signal of other TV standard such as a PAL system signal is alsoprocessed by a circuit made of a similar structure and is transmitted toa liquid crystal panel.

As shown in FIG. 18B, signals from a laser disc or BS (satellitebroadcasting) are transmitted as a Y (brightness) signal 70 and a C(color) signal 71. These are processed by the RGB separation circuit 64to separate the signals into an R signal 72, a G signal 73, and a Bsignal 74. Besides, a horizontal synchronization signal 75 and avertical synchronization signal 76 are also formed.

These RGB signals, and horizontal and vertical synchronization signalsare transmitted to the respective system circuits shown in theembodiments 15 to 18, are transmitted to the driving circuit of theliquid crystal panel, and are restored as a picture by the pixel matrixcircuit.

Embodiment 20

In this embodiment, a constructive example of a process for forming RGBsignals inputted into the system structure shown in the embodiments 15to 18 will be described with reference to a block diagram shown in FIG.19. In this embodiment, which the embodiment 19, an example of circuitstructure corresponding to digital broadcasting in U.S. and the like(corresponding to ATV) will be described.

A video signal 80 is a signal obtained by applying various frequencyconversion processes to a video signal received from an antenna. Thissignal is modulated to the original frequency by a VSB (or QAM)demodulation circuit 81. Then, the signal is restored to a coded signalby a transport decoder 82.

The thus processed signal is inputted into an MPEG2 (decoder) 83, and afrequency band is expanded. The signal is converted into a desiredformat signal by a format conversion circuit 84, and further, an Rsignal 85, a G signal 86, a B signal 87, a horizontal synchronizationsignal 88, and a vertical synchronization signal 89 are formed.

Since digital signals are processed up to here, in the case where ananalog signal is finally desired, it is appropriate that a D/A converter(not shown) is disposed after the format conversion circuit 84.

The video signal obtained in the manner described above is processed bythe system shown in the embodiments 15 to 18. The process so far iscarried out in the IC chip, and it is appropriate that the video signalprocessed in the IC chip is transmitted to the source/gate drivingcircuits formed of TFTs on the substrate.

Incidentally, the TFT in this embodiment includes both a top gate typeTFT and a bottom gate type TFT.

Embodiment 21

In this embodiment, a manufacturing step (multifaced production step) inthe case where a plurality of liquid crystal panels are produced from alarge substrate, will be described with reference to FIG. 20. In thisembodiment, a case where four liquid crystal panels are manufacturedfrom a large square substrate is given as an example.

FIG. 20A shows a step of dividing large substrates of the same size,bonded to each other in a cell assembling step. In FIG. 20A, 1501denotes a seal material (sealing material), and a liquid crystalmaterial is sealed inside of the enclosure of the sealing material. Inthis embodiment, first, as shown in FIG. 20A, the surface on which aliquid crystal injection port 1502 is formed, is divided into parts by ascriber.

The scriber is a device in which after a thin groove (scribe groove) isformed in a substrate, a small impact is given to the substrate togenerate a break (crack) along the groove so that the substrate isdivided into parts.

Other than the scriber, a dicer is known as a device of cutting asubstrate. The dicer is a device in which a hard cutter (dicing saw) ismade to rotate at a high speed to divide a substrate into parts.However, since it is necessary to sprinkle a large amount of water whenusing the dicer in order to suppress heat and polishing powder, thedicer can not be used in the state of FIG. 20A in which the liquidcrystal injection port is open, because water enters the liquid crystalinjection port.

In the step of FIG. 20A, since the scribe groove is formed in thevicinity of the surface of the substrate, scribe grooves are formed inthe side of the first substrate (substrate at the side where TFTs aremanufactured) 1503 and the side of the second substrate (opposite sidesubstrate) 1504 to divide the substrates into parts. This situation willbe described with reference to FIGS. 20B and 20C.

FIG. 20B is a view of FIG. 20A seen in the direction indicated by anarrow. First, in FIG. 20B, as indicated by arrows, scribe grooves 1505to 1508 are formed from both sides of the first substrate 1503 and thesecond substrate 1504.

At this time, as shown in FIG. 20B, the scribe groove 1508 formed in thefirst substrate 1503 and the scribe groove 1506 formed in the secondsubstrate 1504 are aligned to each other. Thus, the structure of thepresent invention (structure in which edges are trued up each other) canbe realized.

At this time, the scribe grooves 1505 and 1507 are formed only in thesecond substrate 1504. Thus, it is possible to partially remove only apart of the second substrate 1504. By this, a part of the firstsubstrate 1503 is exposed. Cutting lines by the scriber are denoted by1520.

After the formation of the scribe grooves in the manner described aboveis completed, cutting is made the substrate to divide into parts so thatthe state shown in FIG. 20C is obtained. A portion 1509 where the firstsubstrate 1503 is exposed as described above is utilized as a portion towhich an FPC and an IC chip are attached.

When the edges at the side where the liquid crystal injection port 1502is formed are trued up each other between the first substrate and thesecond substrate as in the present embodiment, the manufacturing costcan be decreased. This is because, if the edges are trued up each other,such a state can be attained that the liquid crystal injection port isbrought into contact just with the surface of a liquid crystal in asubsequent liquid crystal injection step, so that the height of theliquid level of the liquid crystal prepared can be suppressed to theminimum. That is, since the liquid crystal can be effectively used,which greatly contributes to lowering of cost.

In this way, the large substrate is divided into three substrates inwhich three liquid crystal panels are made one set. Next, injection andsealing steps of a liquid crystal material are carried out for each ofthese three substrates. Since these steps may follow well-known stepscan be adopted as such steps, the explanation will be omitted.

At this time, it is possible to inject a liquid crystal material to thethree liquid crystal panels at the same time. Of course, it is alsopossible to inject the liquid crystal material to nine liquid crystalpanels at the same time by concurrently making the three substratessubjected to batch processing.

In the manner described above, after the injection step of the liquidcrystal material and the sealing step of a sealing material arecompleted the substrate is divided into parts by a dicer along thedirection of a broken line as shown in FIG. 21. The cutting line by thedicer is denoted by 1512. The reason why a liquid crystal material 1510is sealed prior to this step is to make the dicer usable in thisdividing step. Incidentally, reference numeral 1507 denotes a sealingmaterial for sealing the liquid crystal material.

There are advantages of using the dicer, such that dividing errors arefewer than the scriber so that the yield is high, and that since thefirst substrate and the second substrate can be divided into parts atthe same time, the throughput can be improved.

In this way, nine liquid crystal panels are respectively obtained by thedividing step shown in FIG. 20B. Since this dividing step may be carriedout by the dicer at the same time, there is no troublesomeness unlikethe scriber by which scribing must be made from both sides of asubstrate.

Since, in the present invention, edges of the first substrate and edgesof the second substrate are trued up each other at all edges except anedge which is adjacent to the portion where an IC chip is attached, thedividing step of the liquid crystal panel is completed at the same timeas dividing shown in FIG. 21.

Although dividing by the scriber and dividing by the dicer areselectively used in the dividing step in this embodiment, cares as setforth below must be paid to the way of selection.

First, in the case where the scriber is used, since a crack is generatedby giving an impact to a scribe groove and a substrate is divided intoparts along the crack, stress is apt to be applied to a circuit element(TFT, etc.) formed on the substrate at the time of dividing. Since thestress applied to the circuit element may cause deterioration ofcharacteristics of the element, it is not preferable.

Thus, in the case where a circuit requiring a high operating speed isconstructed in the vicinity of a divided surface, since stress has avery bad influence, it is preferable to avoid dividing by the scriberand to carry out dividing by the dicer. In other words, it is desirablethat in the case where dividing is carried out in the vicinity of acircuit susceptible to an influence of stress, the dicer should be usedif possible, and only in the case where dividing is carried out in thevicinity of a circuit which does not receive an influence of stress verymuch, the scriber is used.

For example, if a driving circuit formed by TFTs on a substrate iscovered with a liquid crystal material, it does not easily receivestress. Thus, in the case where a driving circuit is formed in theregion surrounded by a sealing material for sealing a liquid crystal,even if the scriber is used, the stress is not easily transferred. Ifthe dicer is used, even if such a structure is adopted that a liquidcrystal layer is arranged only on a pixel matrix circuit and the liquidcrystal layer does not exist on a driving circuit, stress at dividing isnot easily applied.

As described above, it is very effective to selectively use dividing bythe scriber and dividing by the dicer according to what circuit isdisposed in the vicinity of the substrate surface to be divided. In thecase where the scriber and dicer are selectively used as in thisembodiment, such cares have a very important meaning.

Incidentally, the TFT in this embodiment includes both a top gate typeTFT and a bottom gate type TFT.

Embodiment 22

The liquid crystal module of the present invention can be used as adisplay for various electric equipments. The electric equipment cited inthis embodiment is defined as a product incorporating an electroopticaldevice typified by a liquid crystal module.

Such an electric equipment includes a video camera, a still camera, aprojector, a projection TV, a head mount display, a car navigationsystem, a personal computer, a portable information terminal (mobilecomputer, portable telephone, etc.), and the like. An example is shownin FIG. 22.

FIG. 22A shows a portable telephone which is constituted by a main body2001, an audio output portion 2002, an audio input portion 2003, adisplay device 2004, an operation switch 2005, and an antenna 2006. Thepresent invention can be applied to the display device 2004 and thelike.

FIG. 22B shows a video camera which is constituted by a main body 2101,a display device 2102, an audio input portion 2103, an operation switch2104, a battery 2105, and an image receiving portion 2106. The presentinvention can be applied to the display device 2102.

FIG. 22C shows a mobile computer which is constituted by a main body2201, a camera portion 2202, an image receiving portion 2203, anoperation switch 2204, and a display device 2205. The present inventioncan be applied to the display device 2205 and the like.

FIG. 22D shows a head mount display which is constituted by a main body2301, a display device 2302, and a band portion 2303. The presentinvention can be applied to the display device 2302.

FIG. 22E shows a rear type projector which is constituted by a main body2401, a light source 2402, a display device 2403, a polarizing beamsplitter 2404, reflectors 2405 and 2406, and a screen 2407. The presentinvention can be applied to the display device 2403.

FIG. 22F shows a front type projector which is constituted by a mainbody 2501, a light source 2502, a display device 2503, an optical system2504, and a screen 2505. The present invention can be applied to thedisplay device 2503.

As described above, the scope of application of the present invention isvery wide, and can be applied to an electric equipment of any field.Especially, it can be said that the present invention is very effectivefor an electric equipment that gives priority to portability.

For example, since various kinds of signal processing can be carried outby an IC chip, almost all functions of an electric equipment arepractically performed only by a liquid crystal module. That is, anelectric equipment such as a card type mobile computer can also berealized.

In the present invention, since a substrate at a side where a TFT ismanufactured and an opposite substrate are bonded to each other in sucha manner that the edges thereof are made as flush as possible, and an ICchip is attached to an FPC attaching portion, it is possible toconstitute a very compact liquid crystal module.

Thus, since an IC chip integration type system panel can be realizedwith a minimum size, it is possible to realize a liquid crystal modulewhich is very compact and has multifunctionality. This directlycontributes to miniaturization and lightening (improvement inportability) of an electric equipment.

In the case where a pixel matrix circuit and a driving circuit areconstituted by bottom gate type TFTs (especially, reverse stagger typeTFTs), since they can be formed at a low manufacturing cost, it isexpected that the cost of the liquid crystal module can be lowered, andfurther, the cost of the electric equipment can be lowered.

1. A method of manufacturing a semiconductor device comprising the stepsof: forming a semiconductor film comprising amorphous silicon on aninsulating surface, the semiconductor film comprising a region to becomea channel formation region of a transistor; providing at least a part ofsaid semiconductor film with a material for promoting crystallization ofsilicon, the material comprising a metal; crystallizing thesemiconductor film by a first heat treatment; introducing an impurityselectively into a portion of the crystallized semiconductor film;performing a second heat treatment so that the metal contained at leastin the region to become a channel formation region moves into theportion where the impurity is selectively introduced; and removing atleast the portion of the crystallized semiconductor film to form asemiconductor layer including the region to become a channel formationregion.
 2. The method according to claim 1 wherein the metal is selectedfrom the group consisting of cobalt, iron, palladium, platinum, copper,gold, germanium, lead, indium and nickel.
 3. The method according toclaim 1 wherein the material for promoting crystallization of silicon isprovided by applying a liquid which contains the material onto thesemiconductor film.
 4. The method according to claim 1 wherein theimpurity is phosphorous.
 5. The method according to claim 1 wherein theimpurity is introduced by ion implantation or ion doping.
 6. A method ofmanufacturing a semiconductor device comprising the steps of: forming asemiconductor film comprising amorphous silicon on an insulatingsurface, the semiconductor film comprising a region to become a channelformation region of a transistor; providing an entire upper surface ofsaid semiconductor film with a material for promoting crystallization ofsilicon, the material comprising a metal; crystallizing thesemiconductor film by a first heat treatment; introducing an impurityselectively into a portion of the crystallized semiconductor film;performing a second heat treatment so that the metal contained at leastin the region to become a channel formation region moves into theportion where the impurity is selectively introduced; and removing atleast the portion of the crystallized semiconductor film to form asemiconductor layer including the region to become a channel formationregion.
 7. The method according to claim 6 wherein the metal is selectedfrom the group consisting of cobalt, iron, palladium, platinum, copper,gold, germanium, lead, indium and nickel.
 8. The method according toclaim 6 wherein the material for promoting crystallization of silicon isprovided by applying a liquid which contains the material onto thesemiconductor film.
 9. The method according to claim 6 wherein theimpurity is phosphorous.
 10. The method according to claim 6 wherein theimpurity is introduced by ion implantation or ion doping.
 11. A methodof manufacturing a semiconductor device comprising the steps of: forminga gate electrode; forming a gate insulating film over the gateelectrode; forming a semiconductor film comprising amorphous siliconover the gate insulating film, the semiconductor film comprising aregion to become a channel formation region of a transistor wherein theregion overlaps with the gate electrode; providing at least a part ofsaid semiconductor film with a material for promoting crystallization ofsilicon, the material comprising a metal; crystallizing thesemiconductor film by a first heat treatment; introducing an impurityselectively into a portion of the crystallized semiconductor film;performing a second heat treatment so that the metal contained at leastin the region to become a channel formation region moves into theportion where the impurity is selectively introduced; and removing atleast the portion of the crystallized semiconductor film to form asemiconductor layer including the region to become a channel formationregion.
 12. The method according to claim 11 wherein the metal isselected from the group consisting of cobalt, iron, palladium, platinum,copper, gold, germanium, lead, indium and nickel.
 13. The methodaccording to claim 11 wherein the material for promoting crystallizationof silicon is provided by applying a liquid which contains the materialonto the semiconductor film.
 14. The method according to claim 11wherein the impurity is phosphorous.
 15. The method according to claim11 wherein the impurity is introduced by ion implantation or ion doping.